It is often necessary in a data processing system to read an input data signal from a peripheral device which does not provide a synchronized clock signal. Such a situation may occur, for example, at the interface between a disk drive controller and a disk drive, or at the interface of an asynchronous communications controller and its associated asynchronous communication device. To enable reading of the input signal, a local oscillator must normally be synchronized to transitions found in the input signal itself.
With the typical scenario, local oscillator synchronization is achieved by using an input signal which has two portions. A preamble portion, consisting of closely spaced transitions created by an alternating pattern of logical ones and logical zeros, precedes a data portion, which contains the information to be read. The preamble portion is fed to a phase locked loop (PLL). As is well known a PLL provides a continuous output signal which is phase and frequency locked to its input signal. Phase and frequency lock will occur if the preamble portion is sufficiently long in time to guarantee that the loop reaches a stable state. A suitable clock signal synchronized to the input signal is thus provided at the output of the phase locked loop once the stable state is reached.
A critical design decision in this situation is selecting the phase locked loop bandwidth, since the maximum possible time that it can take for the loop to lock, called the settling time, is inversely proportional to the loop bandwidth. Thus, the larger the loop bandwidth, the shorter the preamble portion can be, and the more time can be spent reading data. Unfortunately, loop bandwidth is also directly proportional to noise susceptibility. Thus, the wider the bandwidth of the loop, the smaller its tolerance to noise in the data portion.
One way to avoid this problem has been to begin with a relatively high loop bandwidth while the PLL is locking to the preamble. Before the end of the preamble, a narrower bandwidth loop filter is switched in. This arrangement provides both the advantages of fast settling time during lock acquisition, and greatest noise immunity after the PLL has locked, while the data is being read. This switch to a narrower bandwidth also helps noise immunity because the signal to noise ratio usually decreases during the data portion due to intersymbol interference.
While this approach has been found adequate in most situations, it is not generally known that other problems exist. One such problem is that a noise pulse occurring just before the end of the preamble may cause a large loop error. Because the loop bandwidth is then narrowed, this large loop error can take a very long time to settle out, during which time the loop is not completely locked. This translates into increased occurrence of data recovery errors. When data is lost, of course, the peripheral must be re-accessed, thereby increasing the overall data read time.
A second problem is caused by the act of changing the loop bandwidth itself. Because this normally involves switching circuit components in and out of the loop, any resulting switching transients often are large enough to perturb the loop. The error thus caused must also be corrected at the lower bandwidth, which takes a much longer time than if the bandwidth had never been decreased.
The first problem is a result of changes in the signal fed to the input of the loop. The latter problem is caused by changes in the transfer function of the loop as its bandwidth changes. Another way to understand this is to consider that the frequency-domain response of a system depends upon the product of the frequency-domain representation of its input signal and the system transfer function. Changes in either the input signal or the system transfer function thus affect the loop's output signal.
In applications such as disk drive controllers, phase synchronization must be reacquired every time a different sector on the disk is selected for access. Since the time spent reading and locking to the preamble portion is time not spent reading data, the need for long preambles can adversely affect the data transfer rate of the disk drive. Perhaps even more importantly in disk drive applications, the need for longer preambles decreases the usable storage capacity of the drive.